dm代表什么

lib/Target/AArch64/AArch64.td
244 ↗	(On Diff #61191)	Isn't it even remotely similar to an A53/A57?
lib/Target/AArch64/AArch64Subtarget.cpp
74 ↗	(On Diff #61191)	Nit: This could be a fall-through for all remaining cases...

pgode marked 2 inline comments as done.Jun 20 2016, 3:17 AM

pgode added inline comments.

lib/Target/AArch64/AArch64.td
244 ↗	(On Diff #61191)	This processor is similar to A57. This patch is for introducing Vulcan in LLVM. We plan to submit the Vulcan scheduler model in subsequent patches, hence 'NoSchedModel.
lib/Target/AArch64/AArch64Subtarget.cpp
74 ↗	(On Diff #61191)	We plan to add Vulcan specific details in subsequent patches under this case. Please let me know if that is ok.

Makes sense. LGTM, thanks!

This revision is now accepted and ready to land.Jun 20 2016, 3:20 AM

Closed by commit rL273148: [AARCH64] Add support for Broadcom Vulcan (authored by pgode). · Explain WhyJun 20 2016, 4:20 AM

This revision was automatically updated to reflect the committed changes.

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Revision Contents

Path

Size

llvm/

trunk/

include/

llvm/

Support/

AArch64TargetParser.def

2 lines

lib/

Target/

AArch64/

AArch64.td

9 lines

AArch64Subtarget.h

3 lines

AArch64Subtarget.cpp

1 line

test/

CodeGen/

AArch64/

cpus.ll

1 line

remat.ll

1 line

Diff 61246

llvm/trunk/include/llvm/Support/AArch64TargetParser.def

	Show First 20 Lines ? Show All 59 Lines ? ▼ Show 20 Lines
	AARCH64_CPU_NAME("cortex-a73", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,			AARCH64_CPU_NAME("cortex-a73", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
	(AArch64::AEK_SIMD \| AArch64::AEK_CRC \| AArch64::AEK_CRYPTO))			(AArch64::AEK_SIMD \| AArch64::AEK_CRC \| AArch64::AEK_CRYPTO))
	AARCH64_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,			AARCH64_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
	(AArch64::AEK_SIMD \| AArch64::AEK_CRYPTO))			(AArch64::AEK_SIMD \| AArch64::AEK_CRYPTO))
	AARCH64_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,			AARCH64_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
	(AArch64::AEK_SIMD \| AArch64::AEK_CRC \| AArch64::AEK_CRYPTO))			(AArch64::AEK_SIMD \| AArch64::AEK_CRC \| AArch64::AEK_CRYPTO))
	AARCH64_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,			AARCH64_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
	(AArch64::AEK_SIMD \| AArch64::AEK_CRC \| AArch64::AEK_CRYPTO))			(AArch64::AEK_SIMD \| AArch64::AEK_CRC \| AArch64::AEK_CRYPTO))
				AARCH64_CPU_NAME("vulcan", AK_ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false,
				(AArch64::AEK_SIMD \| AArch64::AEK_CRC \| AArch64::AEK_CRYPTO))
	// Invalid CPU			// Invalid CPU
	AARCH64_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, AArch64::AEK_INVALID)			AARCH64_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, AArch64::AEK_INVALID)
	#undef AARCH64_CPU_NAME			#undef AARCH64_CPU_NAME

llvm/trunk/lib/Target/AArch64/AArch64.td

Show First 20 Lines ? Show All 209 Lines ? ▼ Show 20 Lines	def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
FeatureFPARMv8,		FeatureFPARMv8,
FeatureMergeNarrowLd,		FeatureMergeNarrowLd,
FeatureNEON,		FeatureNEON,
FeaturePerfMon,		FeaturePerfMon,
FeaturePostRAScheduler,		FeaturePostRAScheduler,
FeaturePredictableSelectIsExpensive		FeaturePredictableSelectIsExpensive
]>;		]>;

		def ProcVulcan : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
		"Broadcom Vulcan processors", [
		FeatureFPARMv8,
		FeatureNEON,
		FeatureCrypto,
		FeatureCRC,
		HasV8_1aOps]>;

def : ProcessorModel<"generic", NoSchedModel, [		def : ProcessorModel<"generic", NoSchedModel, [
FeatureCRC,		FeatureCRC,
FeatureFPARMv8,		FeatureFPARMv8,
FeatureNEON,		FeatureNEON,
FeaturePerfMon,		FeaturePerfMon,
FeaturePostRAScheduler		FeaturePostRAScheduler
]>;		]>;

// FIXME: Cortex-A35 is currently modelled as a Cortex-A53		// FIXME: Cortex-A35 is currently modelled as a Cortex-A53
def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;		def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;		def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;		def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
// FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.		// FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;		def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA57]>;		def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA57]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;		def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;		def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;		def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
		def : ProcessorModel<"vulcan", NoSchedModel, [ProcVulcan]>;

//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
// Assembly parser		// Assembly parser
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

def GenericAsmParserVariant : AsmParserVariant {		def GenericAsmParserVariant : AsmParserVariant {
int Variant = 0;		int Variant = 0;
string Name = "generic";		string Name = "generic";
Show All 37 Lines

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

	Show All 35 Lines
	public:			public:
	enum ARMProcFamilyEnum : uint8_t {			enum ARMProcFamilyEnum : uint8_t {
	Others,			Others,
	CortexA35,			CortexA35,
	CortexA53,			CortexA53,
	CortexA57,			CortexA57,
	Cyclone,			Cyclone,
	ExynosM1,			ExynosM1,
	Kryo			Kryo,
				Vulcan
	};			};

	protected:			protected:
	/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.			/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
	ARMProcFamilyEnum ARMProcFamily = Others;			ARMProcFamilyEnum ARMProcFamily = Others;

	bool HasV8_1aOps = false;			bool HasV8_1aOps = false;
	bool HasV8_2aOps = false;			bool HasV8_2aOps = false;
	▲ Show 20 Lines ? Show All 203 Lines ? Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

Show First 20 Lines ? Show All 65 Lines ? ▼ Show 20 Lines	void AArch64Subtarget::initializeProperties() {
case ExynosM1:		case ExynosM1:
PrefFunctionAlignment = 4;		PrefFunctionAlignment = 4;
PrefLoopAlignment = 3;		PrefLoopAlignment = 3;
break;		break;
case Kryo:		case Kryo:
MaxInterleaveFactor = 4;		MaxInterleaveFactor = 4;
VectorInsertExtractBaseCost = 2;		VectorInsertExtractBaseCost = 2;
break;		break;
		case Vulcan: break;
case CortexA35: break;		case CortexA35: break;
case CortexA53: break;		case CortexA53: break;
case Others: break;		case Others: break;
}		}
}		}

AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,		AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,		const std::string &FS,
▲ Show 20 Lines ? Show All 85 Lines ? Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/cpus.ll

	; This tests that llc accepts all valid AArch64 CPUs			; This tests that llc accepts all valid AArch64 CPUs


	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 \| FileCheck %s
				; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=vulcan 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 \| FileCheck %s --check-prefix=INVALID			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 \| FileCheck %s --check-prefix=INVALID

	; CHECK-NOT: {{.*}} is not a recognized processor for this target			; CHECK-NOT: {{.*}} is not a recognized processor for this target
	; INVALID: {{.*}} is not a recognized processor for this target			; INVALID: {{.*}} is not a recognized processor for this target

	define i32 @f(i64 %z) {			define i32 @f(i64 %z) {
	ret i32 0			ret i32 0
	}			}

llvm/trunk/test/CodeGen/AArch64/remat.ll

	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s \| FileCheck %s
				; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=vulcan -o - %s \| FileCheck %s

	%X = type { i64, i64, i64 }			%X = type { i64, i64, i64 }
	declare void @f(%X*)			declare void @f(%X*)
	define void @t() {			define void @t() {
	entry:			entry:
	%tmp = alloca %X			%tmp = alloca %X
	call void @f(%X* %tmp)			call void @f(%X* %tmp)
	; CHECK: add x0, sp, #8			; CHECK: add x0, sp, #8
	; CHECK-NOT: mov			; CHECK-NOT: mov
	; CHECK-NEXT: bl f			; CHECK-NEXT: bl f
	call void @f(%X* %tmp)			call void @f(%X* %tmp)
	; CHECK: add x0, sp, #8			; CHECK: add x0, sp, #8
	; CHECK-NOT: mov			; CHECK-NOT: mov
	; CHECK-NEXT: bl f			; CHECK-NEXT: bl f
	ret void			ret void
	}			}

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dm代表什么

[AARCH64] Add support for Broadcom VulcanClosedPublic

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Revision Contents

Diff 61246

llvm/trunk/include/llvm/Support/AArch64TargetParser.def

llvm/trunk/lib/Target/AArch64/AArch64.td

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

llvm/trunk/test/CodeGen/AArch64/cpus.ll

llvm/trunk/test/CodeGen/AArch64/remat.ll

[AARCH64] Add support for Broadcom Vulcan
ClosedPublic